Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

ABSTRACT

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si 1-x Ge x . The highest layer may be of the form Si 1-y Ge y  on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si 1-z Ge z  on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional application of U.S. patent application Ser. No.11/078,267, filed Mar. 11, 2005.

BACKGROUND

This invention relates generally to the fabrication of integratedcircuits.

To increase performance of NMOS and PMOS deep sub-micron transistors inCMOS technology, current state-of-the-art technology uses compressivestress in the channel of the PMOS transistors, and tensile stress in thecase of NMOS transistors. This is usually achieved by substrate inducedstrain which is a very expensive technology option and is also difficultto implement using a single substrate approach.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an enlarged, cross-sectional view of an NMOS transistor at anearly stage of manufacture;

FIG. 2 is an enlarged, cross-sectional view of a PMOS transistor at anearly stage of manufacture;

FIG. 3 is an enlarged, cross-sectional view at a stage subsequent to thestage shown in FIG. 1 in accordance with one embodiment of the presentinvention;

FIG. 4 is an enlarged, cross-sectional view at a stage subsequent to thestage shown in FIG. 2 in accordance with one embodiment of the presentinvention;

FIG. 5 is an enlarged, cross-sectional view at a stage subsequent to thestage shown in FIG. 3 in accordance with one embodiment of the presentinvention;

FIG. 6 is an enlarged, cross-sectional view at a stage subsequent to thestage shown in FIG. 4 in accordance with one embodiment of the presentinvention;

FIG. 7 is an enlarged, cross-sectional view at a stage subsequent to thestage shown in FIG. 6 in accordance with one embodiment of the presentinvention;

FIG. 8 is an enlarged, cross-sectional view at a stage subsequent to thestage shown in FIG. 7 in accordance with one embodiment of the presentinvention;

FIG. 9 is an enlarged, cross-sectional view at a stage subsequent to thestage shown in FIG. 8 in accordance with one embodiment of the presentinvention;

FIG. 10 is an enlarged, cross-sectional view at a stage subsequent tothe stage shown in FIG. 9 in accordance with one embodiment of thepresent invention; and

FIG. 11 is an enlarged, cross-sectional view at a stage subsequent tothe stage shown in FIG. 5 in accordance with one embodiment of thepresent invention.

DETAILED DESCRIPTION

Referring to FIG. 1, a silicon substrate 12 may be covered by a gradedbuffer layer 14. The buffer layer 14 may be formed of silicon germaniumof the formula Si_(1-x)Ge_(x) where x is from 0.05 to 0.3. In oneembodiment, the buffer layer 14 may be epitaxially grown, whilegradually increasing the concentration of germanium. Thus, the germaniumconcentration is highest at the top of the layer 14, lowest at thebottom, and linearly increases from bottom to top in one embodiment.

Over the layer 14 may be deposited a constant concentration silicongermanium buffer layer 16. In one embodiment of the present invention,this layer 16 may have a thickness of from 2000 to 10,000 Angstroms. Thelayer 16 may have a constant germanium concentration substantially equalto that of the highest germanium level of the layer 14, in oneembodiment.

A tensile strained silicon layer 18 is formed thereover. Shallow trenchisolations 20 may be provided as well. In one embodiment of the presentinvention, the structure 10 b, shown in FIG. 1, will be utilized to formboth NMOS and PMOS transistors of a complementary metal oxidesemiconductor integrated circuit technology.

The gradient of germanium in the graded buffer layer 14 can varydepending on the thickness and final germanium concentration. In someembodiments, the concentration of germanium in the graded layer 14extends from about zero percent at the bottom to about 40 percent at thetop. Other percentages may be utilized in different situations. Thelayer 14 functions to achieve a relaxed silicon germanium layer and toreduce dislocation formation due to mismatch in the lattice constraintsbetween silicon and the silicon germanium. The constant germaniumconcentration silicon germanium buffer layer 16 further stabilizes thestructure.

The tensile strained silicon layer 18 may be grown. The strained natureof the layer 18 is limited by the critical layer thickness associatedwith the concentration of germanium in the underlying buffer layer 16.

At the same time, the PMOS structure 10 a may be fabricated, as shown inFIG. 2. The PMOS structure 10 a may initially have the same componentsas the NMOS structure 10 b.

Thereafter, as shown in FIG. 3, a hard mask 21 may be deposited over thetensile strained silicon layer 18 on the NMOS side 10 b and PMOS side 10a.

Then, a hard mask etch and resist removal may be utilized to remove thetensile strained silicon 18 and the hard mask 21 on the PMOS transistorstructure 10 a as shown in FIG. 4. The selective etch may use 5 to 8percent NH₄OH with a pH between about 10.2 and 10.4 at a temperaturebetween 20° C. and 27° C. in one embodiment. The resulting structure hasthe tensile strained silicon removed on the PMOS side 10 a. The NMOSside 10 b is still covered by the hard mask 21 (FIG. 3).

The selective wet etch of the strained silicon layer 18 is such thatnucleophillic binding energy of silicon is surpassed and an etch of thesilicon layer 18 is effected. However, the nucleophillic binding energymay be only about 0.5 kJ/mol too little to solubilize the germanium tothe corresponding aqueous species, so the layer 16 is preserved.

Then, a compressively strained silicon germanium layer 28 is depositedas shown in FIG. 6 on the PMOS side 10 a. The silicon germanium may beof the formula Si_(1-y)Ge_(y), where y is greater than x. The higherconcentration y means the layer 28 has a larger lattice than theunderlying layers, resulting in compressive strain applied upwardly bythe layers 14 and 16 to biaxially compress the layer 28.

The layer 28 may be selectively grown on the PMOS side 10 a only and noton the NMOS side 10 b as indicated in FIG. 5 because only the NMOS side10 b was covered by the hard mask 21 at the time the layer 28 wasdeposited.

The fabrication of the PMOS transistor proceeds as shown in FIGS. 7-11.On both the NMOS and PMOS sides a silicon dioxide gate oxide 30 may bedeposited in one embodiment. The gate oxide 30 may be covered by a gatematerial 34, such as polysilicon, in turn covered by a hard mask 34 forpatterning. Then the gate material 34 and gate oxide 30 are patterned togenerate the FIG. 7 structure on the PMOS side 10 a (and the samestructure is created on the NMOS side 10 b with the layer 18 replacingthe layer 28).

Then, separate tip implants I (FIG. 7) and standard lithographicpatterning form the lightly doped source drain regions 39 on both NMOSand PMOS sides (FIG. 8). A nitride spacer material may be deposited andanisotropically etched on both NMOS and PMOS sides to form the spacers36.

On the PMOS side 10 a only, a trench 24 is formed through the layer 28and into the layer 16, as shown in FIG. 9. The trench 24 may be formedby reactive ion etching using SF₆ chemistry. The etching is constrainedby the isolation 20 on one side and may isotropically undercut the gatestructure on the other side. As a result, an isotropic etch profile maybe achieved on the inward edges of the trench 24 as shown in FIG. 9.During this step the NMOS side 10 a may be covered by an oxide mask (notshown).

Then, an epitaxial silicon germanium source drain 40 may be grown whichfills the trench 24 and extends thereabove as indicated at FIG. 10. Thetrench 24 may be filled using silicon germanium having 10-40 atomicpercent germanium. Source drain doping may be done by insitu dopingusing a diborane source. The epitaxial source drain 40 only grows in thetrench 24 because all other material is masked or covered. The sourcedrain 40 is raised and continues to grow until the facets meet.

The fabrication of the NMOS transistor 10 b, shown in FIG. 11, proceedscorrespondingly. However, a conventionally non-epitaxially grown deepersource drain (not shown) may be created.

The PMOS device 10 a may have both uniaxial compressive stress in thechannel direction and in-plane biaxial compressive stress. TheSi_(1-y)Ge_(y) layer 28 acts as a channel and is grown on a relaxedSi_(1-x)Ge_(x) buffer layer 16 with x less than y to produce in-planebiaxial compressive stress. In addition, a silicon germanium epitaxialsource drain 40 produces uniaxial compressive stress in the channel<110> crystallographic direction. The source drain 40 has a highergermanium concentration than the layer 14 so the source drain 40 pushesinwardly from the sides compressing layer 28. With this combination ofstress, higher mobility and, thus, higher device performance may beachieved compared to using either of the stresses alone in someembodiments.

Once the optimal stress condition is known, the device may be engineeredto produce such stress through an epitaxial silicon germanium sourcedrain 40 and a silicon germanium layered structure. Then, a gradedsilicon germanium buffer layer 14 may be grown on the silicon substrate12 followed by a relaxed Si_(1-x)Ge_(x) layer 16 as shown in FIG. 10.Then, a thin Si_(1-y)Ge_(y) layer 28 is grown to form a biaxialcompressive strained channel.

The uniaxial stress is produced by the epitaxial source drain processusing epitaxial Si_(1-z)Ge_(z) grown in recessed source drain regions40. Selecting the germanium fractions so that x is less than y and z isless than x achieves the desired compressive states.

The mobility gain may remain high even as vertical field (gate field) isapplied in some embodiments. In addition, more head room may be providedto increase performance before the device hits the physical stress limitin some embodiments. With the provision of combined stress, holes maystay in their lowest transport effective mass in the <110> channeldirection where scattering suppression is also the strongest. Siliconband structure has a minimum at the gamma point. It also has twelvewings in (0, +−1, +−1), (+−1, 0, +−1) and (+−1, +−1, 0) directions.Ideally, almost all of the holes are placed in two wings in the (1, −1,0) and (−1, 1, 0) direction to achieve the lowest possible transporteffective mass in the channel direction. This can be achieved byapplying both uniaxial compressive and biaxial compressive stress.

The biaxial compressive stress lowers the energy level of the fourin-plane wings and removes holes from the eight off plane wings, placingthem in the four in-plane wings. The four in-plane wings not only havesmaller effective mass, but also have smaller density states, whichleads to a reduction of scattering. The greatest mobility enhancementhappens when the uniaxial compressive stress along the channel directionis added to the biaxial compressed device.

According to simulation, when hole-optical phonon and surface roughnessscattering occurs, most of the holes stay only in the wings along (1,−1, 0) and (−1, 1, 0), which has the smallest transport effective massin the channel direction. Since only two wings are occupied, the densityof states is also greatly reduced, enhancing scattering suppression. Asa result, the combination stressed device may have higher mobility.

While the present invention has been described with respect to a limitednumber of embodiments, those skilled in the art will appreciate numerousmodifications and variations therefrom. It is intended that the appendedclaims cover all such modifications and variations as fall within thetrue spirit and scope of this present invention.

1. A method comprising: forming a PMOS transistor having both uniaxialcompressive stress in the channel direction and in-plane biaxialcompressive stress, including a first layer under said gate electrode ofSi_(1-y)Ge_(y) and a second layer under said first layer, said secondlayer having Si_(1-x)Ge_(x) where x is less than y.
 2. The method ofclaim 1 including forming a substrate covered by a first layer having anincreasing concentration of germanium extending upwardly through thelayer.
 3. The method of claim 2 including covering said first layer witha second layer of constant germanium concentration.
 4. The method ofclaim 3 including forming a source and drain of epitaxial silicongermanium of the form Si_(1-z)Ge_(z).
 5. The method of claim 4 includingmaking z greater than x and x less than y.
 6. The method of claim 1including forming uniaxial compressive stress in the channel directionby forming a silicon germanium epitaxial source drain.
 7. The method ofclaim 1 including forming in-plane biaxial compressive stress bydepositing a silicon germanium layer as a channel having the formSi_(1-y)Ge_(y) and forming an underlying buffer layer of the formSi_(1-x)Ge_(x) where x is less than y.
 8. The method of claim 1including forming NMOS and PMOS transistors at the same time.
 9. Themethod of claim 8 including forming a graded germanium concentrationsilicon germanium buffer layer, covering said buffer layer with a layerof silicon germanium of constant germanium concentration, and coveringsaid constant germanium concentration layer with a tensile strainedsilicon layer on both the NMOS and PMOS sides.
 10. The method of claim 9including selectively removing the tensile strained biaxial siliconlayer on the PMOS side.
 11. The method of claim 10 including selectivelyremoving the tensile strained silicon layer using about 5 to 8 percentNH₄OH with a pH between about 10.2 and 10.4 at a temperature betweenabout 20° C. and 27° C.
 12. The method of claim 10 including removingsaid tensile strained silicon layer on the PMOS side using an etchantthat solubilizes the tensile strained silicon layer but does notsolubilize underlying layers having higher germanium concentrations.